7/10/2023 0 Comments Dts decoder definitionThese 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. The ADSP-SC57x processor is based on the SHARC+ ® dual-core and the arm ® Cortex ®-A5 core. The ADSP-SC57x/ADSP-2157x processors are members of the SHARC ® family of products.
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